Near-Optimal Thermal Monitoring Framework for Many-Core Systems-on-Chip

PHENIC: Towards Photonic 3D-Network-on-Chip Architecture for High-throughput Many-core Systems-on-Chip

Network-on-chip architectures can improve the scalability, performance, and power efficiency of general multiprocessor systems and application-specific heterogeneous multicore and many-core SoCs (MCSoCs). This interconnection paradigm when combined with 3D integration technology offers advantages over 2D NoC design, such as shorter wire length, higher packing density, and smaller footprint. How...

On-chip Network-enabled Many-core Architectures

Silicon Nanophotonics for Many-Core On-Chip Networks

ion layers of the system Device-level Analysis Network-level Analysis Reliabilitymanagement Solution Device-level Design Network-level Design Statistical T-matrix models of variations Device-level Variation Analysis Pareto-Space Designs

On-Chip Network Designs for Many-Core Computational Platforms

Processor designers have been utilizing more processing elements (PEs) on a single chip to make efficient use of technology scaling and also to speed up system performance through increased parallelism. Networks on-chip (NoCs) have been shown to be promising for scalable interconnection of large numbers of PEs in comparison to structures such as point-to-point interconnects or global buses. Thi...

Programming Framework for Reliable and Efficient Embedded Many-Core Systems

Many-core Systems-on-Chip (SoCs) are of increasing significance in the domain of high-performance embedded computing systems where high performance requirements meet stringent timing constraints. The high computing power offered by many-core SoCs, however, does not necessarily translate into high performance. On the one hand, the use of deep submicrometer process technology to fabricate SoCs im...